In dynamic random access memories (DRAMs) constructed as generally shown in U.S. Pat. No. 4,081,701 (a 16 kbit DRAM) issued to White, McAdams and Redwine and assigned to Texas Instruments, Inc., and in U.S. Pat. No. 4,293,993 (a 64 kbit DRAM) issued to McAlexander, White and Rao and assigned to Texas Instruments, Inc., data is stored in a plurality of memory cells arranged in rows and columns, each storage cell consisting of a single capacitor, and the stored data state represented by either the presence or absence of charge stored by the capacitor. In such devices, differential sense amplifiers are used to sense the data state of an addressed cell by comparing the voltage on the storage capacitor to the voltage on a reference, or dummy, capacitor designed to store charge in such a manner as to represent, to the sense amp, a voltage between a "1" data state and a "0" data state stored on the storage capacitor. The charge stored on the storage and dummy cells induce voltages at the sense amp via conductors which are commonly called bit lines; sensing occurs as one plate of the storage cell capacitor is connected to the bit line at one side of the sense amplifier, and one plate of the dummy cell capacitor is connected to the bit line at the other side of the sense amplifier. Upon sensing the differential voltage between the two bit lines, representative of the differential stored charge between the storage and dummy cell capacitors, the sense amplifier then amplifies the differential voltage to a level detectable by the remainder of the memory circuit, and also restores charge to the storage cell reprsentative of the sensed data state via the bit line connected to the addressed storage cell.
It is desirable to use complementary-metal-oxide-semiconductor (CMOS) technology in the peripheral circuitry of a DRAM for many reasons, including reduction of power cosumption by the device. Accordingly, CMOS sense amplifiers have been designed for use in DRAM devices, as disclosed in U.S. Pat. No. 4,555,777 issued Nov. 26, 1985 and assigned to Texas Instruments, Inc., and as disclosed in copending application Ser. No. 636,938, filed Aug. 2, 1984 by C. Duvvury and assigned to Texas Instruments, Inc. Heretofore, CMOS sense amplifier circuits have consisted primarily of a cross-coupled pair of CMOS inverters, with a first sensing node, i.e., the gates of the transistors of one of the inverters, connected to the bit line associated with the storage cell capacitor and also connected to the output of the second inverter, and with a second sensing node, i.e., the gates of the transistors of the second inverter, connected to the bit line associated with the dummy cell and also connected to the output of the first inverter. However, the bit lines generally have a capacitance which is quite large relative to the storage and dummy cell capacitances. With the bit lines, and the capacitance associated therewith, connected to the sensing nodes of the sense amplifier, the time required to sufficiently amplify the differential voltage of the sensing nodes is dependent upon the time required to charge up these relatively large capacitances.
Therefore, it is an object of this invention to provide a CMOS sense amplifier which senses the differential voltage of the bit lines but which isolates the capacitance of the bit lines from the sensing nodes so that the sensing nodes may be amplified without the loading effect of the bit line capacitance.
It is a further object of this invention to provide a CMOS sense amplifier which has the bit line capacitance isolated from the sensing nodes but which has the bit lines driven responsive to the amplified differential voltage at the sensing nodes in order to restore data to the addressed memory cell.